[all-commits] [llvm/llvm-project] 9cf511: [RISCV] Add intrinsics for vector AMO operations

[ShihPo Hung via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 9cf511aa08ae2a5b94e9cefe3fc60cc33358519b
      https://github.com/llvm/llvm-project/commit/9cf511aa08ae2a5b94e9cefe3fc60cc33358519b
  Author: ShihPo Hung <shihpo.hung at sifive.com>
  Date:   2021-01-18 (Mon, 18 Jan 2021)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll

  Log Message:
  -----------
  [RISCV] Add intrinsics for vector AMO operations

Add vamoswap, vamoadd, vamoxor, vamoand, vamoor,
    vamomin, vamomax, vamominu, vamomaxu intrinsics.

Reviewed By: craig.topper, khchen

Differential Revision: https://reviews.llvm.org/D94589