[all-commits] [llvm/llvm-project] 383b65: [RISCV] Use tail agnostic policy for instructions ...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 383b6501ffedc85c2ecfaa7852ec1a9e9c374e3f
      https://github.com/llvm/llvm-project/commit/383b6501ffedc85c2ecfaa7852ec1a9e9c374e3f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-17 (Sun, 17 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll

  Log Message:
  -----------
  [RISCV] Use tail agnostic policy for instructions with tied defs if the use operand is IMPLICIT_DEF.

The vcompress intrinsic is defined such that it requires a tail
undisturbed policy. This patch makes it so we can use the tail
agnostic policy if the user has passed vundefined to the dest
operand.

We need to do something similar for masked policy, but we need
annotation of which instructions use the mask policy first.

Not sure if this is sufficient for scheduling or if we'll need to
select different pseudos that don't have a tied def.

Reviewed By: evandro

Differential Revision: https://reviews.llvm.org/D94566