[all-commits] [llvm/llvm-project] 5cf73d: [RISCV] Convert most of the information about RVV ...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 5cf73dca77e52f54c893d2c5fc2f56a5f2764f7d
      https://github.com/llvm/llvm-project/commit/5cf73dca77e52f54c893d2c5fc2f56a5f2764f7d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-10 (Sun, 10 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
    M llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

  Log Message:
  -----------
  [RISCV] Convert most of the information about RVV Pseudos into bits in TSFlags.

This patch moves all but the BaseInstr to bits in TSFlags.

For the index fields, we can just use a bit to indicate their presence.
The locations of the operands are well defined.

This reduces the llc binary by about 32K on my build. It also
removes the binary search of the table from the custom inserter.
Instead we just check that the SEW op is present.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D94375