[all-commits] [llvm/llvm-project] 6fc7a9: [RISCV] Change ConstraintMask in RISCVII enum to b...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6fc7a92eeeb5c47754b875bf6cf1b84687ebe693
      https://github.com/llvm/llvm-project/commit/6fc7a92eeeb5c47754b875bf6cf1b84687ebe693
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-09 (Sat, 09 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

  Log Message:
  -----------
  [RISCV] Change ConstraintMask in RISCVII enum to be shifted left. NFC

This makes the mask align with the position of the bits in TSFlags
which is a little more logical.

I might be adding more fields to TSFlags and some might be single
bits where just ANDing with mask to test the bit would make sense.

While there rename TargetFlags in validateInstruction to reflect
that it's just the constraint bits.