[all-commits] [llvm/llvm-project] 41d060: [SelectionDAG] Teach isConstOrConstSplat about ISD...

[Fraser Cormack via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 41d06095b0d22c940538f10a5fb0f44d43769e7f
      https://github.com/llvm/llvm-project/commit/41d06095b0d22c940538f10a5fb0f44d43769e7f
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-01-09 (Sat, 09 Jan 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares-with-imm.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll

  Log Message:
  -----------
  [SelectionDAG] Teach isConstOrConstSplat about ISD::SPLAT_VECTOR

This improves llvm::isConstOrConstSplat by allowing it to analyze
ISD::SPLAT_VECTOR nodes, in order to allow more constant-folding of
operations using scalable vector types.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94168


  Commit: b02eab9058e58782fca32dd8b1e53c27ed93f866
      https://github.com/llvm/llvm-project/commit/b02eab9058e58782fca32dd8b1e53c27ed93f866
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-01-09 (Sat, 09 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    A llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll

  Log Message:
  -----------
  [RISCV] Add scalable vector icmp ISel patterns

Original patch by @rogfer01.

The RVV integer comparison instructions are defined in such a way that
many LLVM operations are defined by using the "opposite" comparison
instruction and swapping the operands. This is done in this patch in
most cases, except for the mappings where the immediate range must be
adjusted to accomodate:

    va < i --> vmsle{u}.vi vd, va, i-1, vm
    va >= i --> vmsgt{u}.vi vd, va, i-1, vm

That is left for future optimization; this patch supports all operations
but in the case of the missing mappings the immediate will be moved to
a scalar register first.

Since there are so many condition codes and operand cases to check, it
was decided to reduce the test burden by only testing the "vscale x 8"
vector types.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Fraser Cormack <fraser at codeplay.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94168


Compare: https://github.com/llvm/llvm-project/compare/03d249396d6b...b02eab9058e5