[all-commits] [llvm/llvm-project] 2f499b: [AMDGPU] Add volatile support to SIMemoryLegalizer

[Tony Tye via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2f499b9affb6797253937eb60760a7d1b60716d7
      https://github.com/llvm/llvm-project/commit/2f499b9affb6797253937eb60760a7d1b60716d7
  Author: Tony <Tony.Tye at amd.com>
  Date:   2021-01-09 (Sat, 09 Jan 2021)

  Changed paths:
    M llvm/docs/AMDGPUUsage.rst
    M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn-ieee.ll
    M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx10-branch-offset-bug.ll
    M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
    M llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
    M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
    M llvm/test/CodeGen/AMDGPU/cc-update.ll
    M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
    M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
    M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
    M llvm/test/CodeGen/AMDGPU/commute_modifiers.ll
    M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
    M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
    M llvm/test/CodeGen/AMDGPU/ds_write2.ll
    M llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
    M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
    M llvm/test/CodeGen/AMDGPU/extload-private.ll
    M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
    M llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll
    M llvm/test/CodeGen/AMDGPU/flat-address-space.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
    M llvm/test/CodeGen/AMDGPU/fma-combine.ll
    M llvm/test/CodeGen/AMDGPU/fmax3.f64.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
    M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
    M llvm/test/CodeGen/AMDGPU/function-args.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
    M llvm/test/CodeGen/AMDGPU/imm16.ll
    M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
    M llvm/test/CodeGen/AMDGPU/load-hi16.ll
    M llvm/test/CodeGen/AMDGPU/load-lo16.ll
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
    M llvm/test/CodeGen/AMDGPU/mad-combine.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
    M llvm/test/CodeGen/AMDGPU/madak.ll
    M llvm/test/CodeGen/AMDGPU/madmk.ll
    A llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
    A llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
    A llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
    A llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
    M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
    M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
    M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
    M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
    M llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll
    M llvm/test/CodeGen/AMDGPU/rsq.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/shl.ll
    M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
    M llvm/test/CodeGen/AMDGPU/sign_extend.ll
    M llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
    M llvm/test/CodeGen/AMDGPU/stack-realign.ll
    M llvm/test/CodeGen/AMDGPU/store-hi16.ll
    M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
    M llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
    M llvm/test/CodeGen/AMDGPU/v_mac.ll
    M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
    M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll

  Log Message:
  -----------
  [AMDGPU] Add volatile support to SIMemoryLegalizer

Treat a non-atomic volatile load and store as a relaxed atomic at
system scope for the address spaces accessed. This will ensure all
relevant caches will be bypassed.

A volatile atomic is not changed and still only bypasses caches upto
the level specified by the SyncScope operand.

Differential Revision: https://reviews.llvm.org/D94214