[all-commits] [llvm/llvm-project] f02e61: Fix MLIR DRR matching when attributes are interlea...

[Mehdi Amini via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f02e61a8b957871292e092aa440964c0f4e2bb21
      https://github.com/llvm/llvm-project/commit/f02e61a8b957871292e092aa440964c0f4e2bb21
  Author: Mehdi Amini <joker.eph at gmail.com>
  Date:   2021-01-08 (Fri, 08 Jan 2021)

  Changed paths:
    M mlir/test/mlir-tblgen/rewriter-indexing.td
    M mlir/tools/mlir-tblgen/RewriterGen.cpp

  Log Message:
  -----------
  Fix MLIR DRR matching when attributes are interleaved with operands

The ODSOperand indexing should ignore the attributes.

Differential Revision: https://reviews.llvm.org/D94281