[all-commits] [llvm/llvm-project] c68fae: [RISCV] Return a vXi1 vector type from getSetCCRes...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c68faed041e664be5b289eae00ee4ca855ddf1c9
      https://github.com/llvm/llvm-project/commit/c68faed041e664be5b289eae00ee4ca855ddf1c9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-06 (Wed, 06 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Return a vXi1 vector type from getSetCCResultType if V extension is enabled.

nvxXi1 types are legal with V extension and that's the result
vmseq/vmsne/vmslt/etc instructions return.

No test cases yet because the setcc isel patterns aren't in
and we'll need more than basic tests to observe this. I locally
tested that this plus D947078, D94168, D94142, and D94149
was enough to be able to handle the overflow result from
llvm.sadd.overflow.