[all-commits] [llvm/llvm-project] cb0c03: [PowerPC] Fix issue where vsrq is given incorrect ...

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  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: cb0c034edc98b32691ea25b70fc3cc2e9d6d2a86
      https://github.com/llvm/llvm-project/commit/cb0c034edc98b32691ea25b70fc3cc2e9d6d2a86
  Author: Stefan Pintilie <stefanp at ca.ibm.com>
  Date:   2021-01-06 (Wed, 06 Jan 2021)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCInstrPrefix.td
    M llvm/test/CodeGen/PowerPC/p10-vector-shift.ll

  Log Message:
  -----------
  [PowerPC] Fix issue where vsrq is given incorrect shift vector

The new Power10 instruction vsrq was being given the wrong shift vector.
The original code assumed that the shift would be found in bits 121 to 127.
This is not correct. The shift is found in bits 57 to 63.
This can be fixed by swaping the first and second double words.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D94113