[all-commits] [llvm/llvm-project] 210bc3: [RISCV] Don't parse 'vmsltu.vi v0, v1, 0' as 'vmsl...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 210bc3dc0eb3550fd99158e5747619ad9e91c548
      https://github.com/llvm/llvm-project/commit/210bc3dc0eb3550fd99158e5747619ad9e91c548
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-05 (Tue, 05 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/test/MC/RISCV/rvv/compare.s

  Log Message:
  -----------
  [RISCV] Don't parse 'vmsltu.vi v0, v1, 0' as 'vmsleu.vi v0, v1, -1'

vmsltu.vi v0, v1, 0 is always false there is no unsigned number
less than 0. vmsleu.vi v0, v1, -1 on the other hand is always true
since -1 will be considered unsigned max and all numbers are <=
unsigned max.

A similar problem exists for vmsgeu.vi v0, v1, 0 which is always true,
but becomes vmsgtu.vi v0, v1, -1 which is always false.

To match the GNU assembler we'll emit vmsne.vv and vmseq.vv with
the same register for these cases instead.

I'm using AsmParserOnly pseudo instructions here because we can't
match an explicit immediate in an InstAlias. And we can't use a
AsmOperand for the zero because the output we want doesn't use an
immediate so there's nowhere to name the AsmOperand we want to use.

To keep the implementations similar I'm also handling signed with
pseudo instructions even though they don't have this issue. This
way we can avoid the special renderMethod that decremented by 1 so
the immediate we see for the pseudo instruction in processInstruction
is 0 and not -1. Another option might have been to have a different
simm5_plus1 operand for the unsigned case or just live with the
immediate being pre-decremented. I felt this way was clearer, but I'm
open to other opinions.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D94035