[all-commits] [llvm/llvm-project] c70771: [RISCV] Match vmslt(u).vx intrinsics with a small ...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c707716c049cd46bd89da102cf9444462487b490
      https://github.com/llvm/llvm-project/commit/c707716c049cd46bd89da102cf9444462487b490
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-05 (Tue, 05 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll

  Log Message:
  -----------
  [RISCV] Match vmslt(u).vx intrinsics with a small immediate to vmsle(u).vx.

There are vmsle(u).vx and vmsle(u).vi instructions, but there is
only vmslt(u).vx and no vmslt(u).vi. vmslt(u).vi can be emulated
for some immediates by decrementing the immediate and using vmsle(u).vi.

To avoid the user needing to know about this, this patch does this
conversion.

The assembler does the same thing for vmslt(u).vi and vmsge(u).vi
pseudoinstructions. There is no vmsge(u).vx intrinsic or
instruction so this patch is limited to vmslt(u).

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D94070