[all-commits] [llvm/llvm-project] dc9ac0: [RISCV] Replace i32 with XLenVT in (add AddrFI, si...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: dc9ac0e8207654e9ad57e7135276c04fdadbe36f
      https://github.com/llvm/llvm-project/commit/dc9ac0e8207654e9ad57e7135276c04fdadbe36f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-04 (Mon, 04 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/vararg.ll

  Log Message:
  -----------
  [RISCV] Replace i32 with XLenVT in (add AddrFI, simm12) isel patterns.

With the i32 these patterns will only fire on RV32, but they
don't look RV32 specific.

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D93843