[all-commits] [llvm/llvm-project] 351c21: [RISCV] Define vector mask-register logical intrin...

[Zakk Chen via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 351c216f36afab3bb88eb74995a39940b85e3812
      https://github.com/llvm/llvm-project/commit/351c216f36afab3bb88eb74995a39940b85e3812
  Author: Zakk Chen <zakk.chen at sifive.com>
  Date:   2020-12-24 (Thu, 24 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vector mask-register logical intrinsics.

Define vector mask-register logical intrinsics and lower them
to V instructions. Also define pseudo instructions vmmv.m
and vmnot.m.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen at sifive.com>

Differential Revision: https://reviews.llvm.org/D93705