[all-commits] [llvm/llvm-project] 1a7ac2: [RISCV] Add ISel support for RVV vector/scalar forms
Fraser Cormack via All-commits
all-commits at lists.llvm.org
Wed Dec 23 12:26:25 PST 2020
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: 1a7ac29a89f8209dda6567a3d48594a618aa1621
https://github.com/llvm/llvm-project/commit/1a7ac29a89f8209dda6567a3d48594a618aa1621
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2020-12-23 (Wed, 23 Dec 2020)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
A llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
A llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll
A llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
A llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll
A llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll
A llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
A llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll
A llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll
Log Message:
-----------
[RISCV] Add ISel support for RVV vector/scalar forms
This patch extends the SDNode ISel support for RVV from only the
vector/vector instructions to include the vector/scalar and
vector/immediate forms.
It uses splat_vector to carry the scalar in each case, except when
XLEN<SEW (RV32 SEW=64) when a custom node `SPLAT_VECTOR_I64` is used for
type-legalization and to encode the fact that the value is sign-extended
to SEW. When the scalar is a full 64-bit value we use a sequence to
materialize the constant into the vector register.
The non-intrinsic ISel patterns have also been split into their own
file.
Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Fraser Cormack <fraser at codeplay.com>
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D93312
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