[all-commits] [llvm/llvm-project] a9f14c: [ARM] Add bank conflict hazarding

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a9f14cdc6203c05425f8b17228ff368f7fd9ae29
      https://github.com/llvm/llvm-project/commit/a9f14cdc6203c05425f8b17228ff368f7fd9ae29
  Author: David Penry <david.penry at arm.com>
  Date:   2020-12-23 (Wed, 23 Dec 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARM.td
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
    M llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
    M llvm/lib/Target/ARM/ARMHazardRecognizer.h
    M llvm/lib/Target/ARM/ARMSubtarget.cpp
    M llvm/lib/Target/ARM/ARMSubtarget.h
    A llvm/test/CodeGen/Thumb2/schedm7-hazard.ll

  Log Message:
  -----------
  [ARM] Add bank conflict hazarding

Adds ARMBankConflictHazardRecognizer. This hazard recognizer
looks for a few situations where the same base pointer is used and
then checks whether the offsets lead to a bank conflict. Two
parameters are also added to permit overriding of the target
assumptions:

arm-data-bank-mask=<int> - Mask of bits which are to be checked for
conflicts.  If all these bits are equal in the offsets, there is a
conflict.
arm-assume-itcm-bankconflict=<bool> - Assume that there will be bank
conflicts on any loads to a constant pool.

This hazard recognizer is enabled for Cortex-M7, where the Technical
Reference Manual states that there are two DTCM banks banked using bit
2 and one ITCM bank.

Differential Revision: https://reviews.llvm.org/D93054