[all-commits] [llvm/llvm-project] efe7f5: [WebAssembly][NFC] Refactor SIMD load/store tableg...

[Thomas Lively via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: efe7f5ede0b3276f3f43daca46410bb7978221fb
      https://github.com/llvm/llvm-project/commit/efe7f5ede0b3276f3f43daca46410bb7978221fb
  Author: Thomas Lively <tlively at google.com>
  Date:   2020-12-22 (Tue, 22 Dec 2020)

  Changed paths:
    M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
    M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

  Log Message:
  -----------
  [WebAssembly][NFC] Refactor SIMD load/store tablegen defs

Introduce `Vec` records, each bundling all information related to a single SIMD
lane interpretation. This lets TableGen definitions take a single Vec parameter
from which they can extract information rather than taking multiple redundant
parameters. This commit refactors all of the SIMD load and store instruction
definitions to use the new `Vec`s. Subsequent commits will similarly refactor
additional instruction definitions.

Differential Revision: https://reviews.llvm.org/D93660