[all-commits] [llvm/llvm-project] 9a8ef9: [RISCV] Define vector compare intrinsics.

Kai Wang via All-commits all-commits at lists.llvm.org
Mon Dec 21 22:36:33 PST 2020


  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 9a8ef927df38a933909a512bf0089a28387ad876
      https://github.com/llvm/llvm-project/commit/9a8ef927df38a933909a512bf0089a28387ad876
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2020-12-22 (Tue, 22 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vector compare intrinsics.

Define vector compare intrinsics and lower them to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang at sifive.com>

Differential Revision: https://reviews.llvm.org/D93368




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