[all-commits] [llvm/llvm-project] 9cf3b1: [RISCV] Define vlxe/vsxe/vsuxe intrinsics.

[Zakk Chen via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 9cf3b1b66650610f22db1c1a4514a860c84c4daa
      https://github.com/llvm/llvm-project/commit/9cf3b1b66650610f22db1c1a4514a860c84c4daa
  Author: Zakk Chen <zakk.chen at sifive.com>
  Date:   2020-12-19 (Sat, 19 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vlxe-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vsuxe-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vsuxe-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vsxe-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vsxe-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vlxe/vsxe/vsuxe intrinsics.

Define vlxe/vsxe intrinsics and lower to vlxei<EEW>/vsxei<EEW>
instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen at sifive.com>

Differential Revision: https://reviews.llvm.org/D93471