[all-commits] [llvm/llvm-project] 69c8d1: [RISCV] Add intrinsics for vsetvli instruction

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 69c8d121f7f22e483e35a3d893052011ee70c23e
      https://github.com/llvm/llvm-project/commit/69c8d121f7f22e483e35a3d893052011ee70c23e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-12-18 (Fri, 18 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
    M llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
    A llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll
    A llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll

  Log Message:
  -----------
  [RISCV] Add intrinsics for vsetvli instruction

This patch adds two IR intrinsics for vsetvli instruction. One to set the vector length to a user specified value and one to set it to vlmax. The vlmax uses the X0 source register encoding.

Clang builtins will follow in a separate patch

Differential Revision: https://reviews.llvm.org/D92973