[all-commits] [llvm/llvm-project] e1c1ad: [ARM] Match dual lane vmovs from insert_vector_elt

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e1c1adf9dc1a6e535ff6a8d5373e968f772e68e1
      https://github.com/llvm/llvm-project/commit/e1c1adf9dc1a6e535ff6a8d5373e968f772e68e1
  Author: David Green <david.green at arm.com>
  Date:   2020-12-18 (Fri, 18 Dec 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/test/CodeGen/Thumb2/active_lane_mask.ll
    M llvm/test/CodeGen/Thumb2/mve-abs.ll
    M llvm/test/CodeGen/Thumb2/mve-div-expand.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
    M llvm/test/CodeGen/Thumb2/mve-minmax.ll
    M llvm/test/CodeGen/Thumb2/mve-neg.ll
    M llvm/test/CodeGen/Thumb2/mve-phireg.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-and.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-not.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-or.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
    M llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
    M llvm/test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll
    M llvm/test/CodeGen/Thumb2/mve-sext.ll
    M llvm/test/CodeGen/Thumb2/mve-shifts.ll
    M llvm/test/CodeGen/Thumb2/mve-simple-arith.ll
    M llvm/test/CodeGen/Thumb2/mve-soft-float-abi.ll
    M llvm/test/CodeGen/Thumb2/mve-vabdus.ll
    M llvm/test/CodeGen/Thumb2/mve-vcmp.ll
    M llvm/test/CodeGen/Thumb2/mve-vcmpr.ll
    M llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
    M llvm/test/CodeGen/Thumb2/mve-vcreate.ll
    M llvm/test/CodeGen/Thumb2/mve-vcvt.ll
    M llvm/test/CodeGen/Thumb2/mve-vdup.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
    M llvm/test/CodeGen/Thumb2/mve-vld2-post.ll
    M llvm/test/CodeGen/Thumb2/mve-vld2.ll
    M llvm/test/CodeGen/Thumb2/mve-vld3.ll
    M llvm/test/CodeGen/Thumb2/mve-vld4-post.ll
    M llvm/test/CodeGen/Thumb2/mve-vld4.ll
    M llvm/test/CodeGen/Thumb2/mve-vmulh.ll
    M llvm/test/CodeGen/Thumb2/mve-vmull-loop.ll
    M llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll
    M llvm/test/CodeGen/Thumb2/mve-vqmovn.ll
    M llvm/test/CodeGen/Thumb2/mve-vqshrn.ll
    M llvm/test/CodeGen/Thumb2/mve-vst2.ll
    M llvm/test/CodeGen/Thumb2/mve-vst3.ll
    M llvm/test/CodeGen/Thumb2/mve-vst4.ll
    M llvm/test/CodeGen/Thumb2/mve-widen-narrow.ll

  Log Message:
  -----------
  [ARM] Match dual lane vmovs from insert_vector_elt

MVE has a dual lane vector move instruction, capable of moving two
general purpose registers into lanes of a vector register. They look
like one of:
  vmov q0[2], q0[0], r2, r0
  vmov q0[3], q0[1], r3, r1
They only accept these lane indices though (and only insert into an
i32), either moving lanes 1 and 3, or 0 and 2.

This patch adds some tablegen patterns for them, selecting from vector
inserts elements. Because the insert_elements are know to be
canonicalized to ascending order there are several patterns that we need
to select. These lane indices are:

3 2 1 0    -> vmovqrr 31; vmovqrr 20
3 2 1      -> vmovqrr 31; vmov 2
3 1        -> vmovqrr 31
2 1 0      -> vmovqrr 20; vmov 1
2 0        -> vmovqrr 20

With the top one being the most common. All other potential patterns of
lane indices will be matched by a combination of these and the
individual vmov pattern already present. This does mean that we are
selecting several machine instructions at once due to the need to
re-arrange the inserts, but in this case there is nothing else that will
attempt to match an insert_vector_elt node.

This is a recommit of 6cc3d80a84884a79967fffa4596c14001b8ba8a3 after
fixing the backward instruction definitions.