[all-commits] [llvm/llvm-project] a89d75: Add intrinsics for saturating float to int casts

[Björn Pettersson via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a89d751fb401540c89189e7c17ff64a6eca98587
      https://github.com/llvm/llvm-project/commit/a89d751fb401540c89189e7c17ff64a6eca98587
  Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
  Date:   2020-12-18 (Fri, 18 Dec 2020)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/include/llvm/CodeGen/ISDOpcodes.h
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/CodeGen/TargetLoweringBase.cpp
    A llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
    A llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
    A llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
    A llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
    A llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
    A llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
    A llvm/test/CodeGen/X86/fptoui-sat-scalar.ll

  Log Message:
  -----------
  Add intrinsics for saturating float to int casts

This patch adds support for the fptoui.sat and fptosi.sat intrinsics,
which provide basically the same functionality as the existing fptoui
and fptosi instructions, but will saturate (or return 0 for NaN) on
values unrepresentable in the target type, instead of returning
poison. Related mailing list discussion can be found at:
https://groups.google.com/d/msg/llvm-dev/cgDFaBmCnDQ/CZAIMj4IBAAJ

The intrinsics have overloaded source and result type and support
vector operands:

    i32 @llvm.fptoui.sat.i32.f32(float %f)
    i100 @llvm.fptoui.sat.i100.f64(double %f)
    <4 x i32> @llvm.fptoui.sat.v4i32.v4f16(half %f)
    // etc

On the SelectionDAG layer two new ISD opcodes are added,
FP_TO_UINT_SAT and FP_TO_SINT_SAT. These opcodes have two operands
and one result. The second operand is an integer constant specifying
the scalar saturation width. The idea here is that initially the
second operand and the scalar width of the result type are the same,
but they may change during type legalization. For example:

    i19 @llvm.fptsi.sat.i19.f32(float %f)
    // builds
    i19 fp_to_sint_sat f, 19
    // type legalizes (through integer result promotion)
    i32 fp_to_sint_sat f, 19

I went for this approach, because saturated conversion does not
compose well. There is no good way of "adjusting" a saturating
conversion to i32 into one to i19 short of saturating twice.
Specifying the saturation width separately allows directly saturating
to the correct width.

There are two baseline expansions for the fp_to_xint_sat opcodes. If
the integer bounds can be exactly represented in the float type and
fminnum/fmaxnum are legal, we can expand to something like:

    f = fmaxnum f, FP(MIN)
    f = fminnum f, FP(MAX)
    i = fptoxi f
    i = select f uo f, 0, i # unnecessary if unsigned as 0 = MIN

If the bounds cannot be exactly represented, we expand to something
like this instead:

    i = fptoxi f
    i = select f ult FP(MIN), MIN, i
    i = select f ogt FP(MAX), MAX, i
    i = select f uo f, 0, i # unnecessary if unsigned as 0 = MIN

It should be noted that this expansion assumes a non-trapping fptoxi.

Initial tests are for AArch64, x86_64 and ARM. This exercises all of
the scalar and vector legalization. ARM is included to test float
softening.

Original patch by @nikic and @ebevhan (based on D54696).

Differential Revision: https://reviews.llvm.org/D54749