[all-commits] [llvm/llvm-project] 4b07c5: [RISCV] Define vlse/vsse intrinsics.

[Zakk Chen via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 4b07c515ef407786a5c2ebc9f7f9d2638eeaf8cf
      https://github.com/llvm/llvm-project/commit/4b07c515ef407786a5c2ebc9f7f9d2638eeaf8cf
  Author: Zakk Chen <zakk.chen at sifive.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vsse-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vlse/vsse intrinsics.

Define vlse/vsse intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen at sifive.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93445