[all-commits] [llvm/llvm-project] 97c006: [AArch64] Add a GPR64x8 register class

[Lucas Duarte Prates via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 97c006aabb6c831d68204bcb4aad8670af695618
      https://github.com/llvm/llvm-project/commit/97c006aabb6c831d68204bcb4aad8670af695618
  Author: Lucas Prates <lucas.prates at arm.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h

  Log Message:
  -----------
  [AArch64] Add a GPR64x8 register class

This adds a GPR64x8 register class that will be needed as the data
operand to the LD64B/ST64B family of instructions in the v8.7-A
Accelerator Extension, which load or store a contiguous range of eight
x-regs. It has to be its own register class so that register allocation
will have visibility of the full set of registers actually read/written
by the instructions, which will be needed when we add intrinsics and/or
inline asm access to this piece of architecture.

Patch written by Simon Tatham.

Reviewed By: ostannard

Differential Revision: https://reviews.llvm.org/D91774