[all-commits] [llvm/llvm-project] dd5281: [RISCV] Define vector mul/div/rem intrinsics.

[Kai Wang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: dd5281e7cce55d64cb0efd272172c1b4f8bf5bb0
      https://github.com/llvm/llvm-project/commit/dd5281e7cce55d64cb0efd272172c1b4f8bf5bb0
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vector mul/div/rem intrinsics.

Define vector mul/div/rem intrinsics and lower them to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang at sifive.com>

Differential Revision: https://reviews.llvm.org/D93380


  Commit: a5e4a513b0410c7ebafc7b8cc00903220536f555
      https://github.com/llvm/llvm-project/commit/a5e4a513b0410c7ebafc7b8cc00903220536f555
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vector widening mul intrinsics.

Define vector widening mul intrinsics and lower them to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang at sifive.com>

Differential Revision: https://reviews.llvm.org/D93381


Compare: https://github.com/llvm/llvm-project/compare/f03609b5c753...a5e4a513b041