[all-commits] [llvm/llvm-project] 15ce0a: [RISCV] Refine vector load/store tablegen pattern, ...

[Zakk Chen via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 15ce0ab7ac46382ec38e7de59ec40c099b85cbf7
      https://github.com/llvm/llvm-project/commit/15ce0ab7ac46382ec38e7de59ec40c099b85cbf7
  Author: Zakk Chen <zakk.chen at sifive.com>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir
    M llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll

  Log Message:
  -----------
  [RISCV] Refine vector load/store tablegen pattern, NFC.

Refine tablegen pattern for vector load/store, and follow
D93012 to separate masked and unmasked definitions for
pseudo load/store instructions.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93284