[all-commits] [llvm/llvm-project] 9e16c5: [AArch64][GlobalISel] Look through a G_ZEXT when t...

Jessica Paquette via All-commits all-commits at lists.llvm.org
Tue Dec 15 15:30:02 PST 2020


  Branch: refs/heads/release/11.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 9e16c5bfae6e8d3cbec74376c2e734e3ff4ba11b
      https://github.com/llvm/llvm-project/commit/9e16c5bfae6e8d3cbec74376c2e734e3ff4ba11b
  Author: Amara Emerson <amara at apple.com>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Look through a G_ZEXT when trying to match shift-extended register offsets.

The G_ZEXT in these cases seems to actually come from a combine that we do but
SelectionDAG doesn't. Looking through it allows us to match "uxtw #2" addressing
modes.

Differential Revision: https://reviews.llvm.org/D91475

(cherry picked from commit 0b6090699ab542cde24be1565b4d97dbad153cba)


  Commit: 280e47ea0e837b809be03f2048ac8abc14dbc387
      https://github.com/llvm/llvm-project/commit/280e47ea0e837b809be03f2048ac8abc14dbc387
  Author: Jessica Paquette <jpaquette at apple.com>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/subreg-copy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Narrow 128-bit regs to 64-bit regs in emitTestBit

When we have a 128-bit register, emitTestBit would incorrectly narrow to 32
bits always. If the bit number was > 32, then we would need a TB(N)ZX. This
would cause a crash, as we'd have the wrong register class. (PR48379)

This generalizes `narrowExtReg` into `moveScalarRegClass`.

This also allows us to remove `widenGPRBankRegIfNeeded` entirely, since
`selectCopy` correctly handles SUBREG_TO_REG etc.

This does create some codegen changes (since `selectCopy` uses the `all`
regclass variants). However, I think that these will likely be optimized away,
and we can always improve the `selectCopy` code. It looks like we should
revisit `selectCopy` at this point, and possibly refactor it into at least one
`emit` function.

Differential Revision: https://reviews.llvm.org/D92707

(cherry picked from commit 195a7af0abb26915f962462f69c0f17e3835f78b)


Compare: https://github.com/llvm/llvm-project/compare/6ec777c2f649...280e47ea0e83


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