[all-commits] [llvm/llvm-project] 19db6a: [RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.

[Kai Wang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 19db6a652b88674b5b0a12eebc4b68244ec88ee4
      https://github.com/llvm/llvm-project/commit/19db6a652b88674b5b0a12eebc4b68244ec88ee4
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2020-12-16 (Wed, 16 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsbc-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang at sifive.com>

Differential Revision: https://reviews.llvm.org/D93175


  Commit: 95795e7a65a7307065d8f6a030ba56d713a77d9a
      https://github.com/llvm/llvm-project/commit/95795e7a65a7307065d8f6a030ba56d713a77d9a
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2020-12-16 (Wed, 16 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vsll/vsrl/vsra intrinsics.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang at sifive.com>

Differential Revision: https://reviews.llvm.org/D93193


  Commit: fd2716456313f2e6067c2aef329ce2b1f6084f63
      https://github.com/llvm/llvm-project/commit/fd2716456313f2e6067c2aef329ce2b1f6084f63
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2020-12-16 (Wed, 16 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vnsrl/vnsra intrinsics.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang at sifive.com>

Differential Revision: https://reviews.llvm.org/D93207


  Commit: 903f2950091a8a97778e558a1e6cea08794a12ce
      https://github.com/llvm/llvm-project/commit/903f2950091a8a97778e558a1e6cea08794a12ce
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2020-12-16 (Wed, 16 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vmin/vminu/vmax/vmaxu intrinsics.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang at sifive.com>

Differential Revision: https://reviews.llvm.org/D93218


  Commit: c1dac6bac5b808a6554181e4fe214f8c7b8e6c50
      https://github.com/llvm/llvm-project/commit/c1dac6bac5b808a6554181e4fe214f8c7b8e6c50
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2020-12-16 (Wed, 16 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vfadd/vfsub/vfrsub intrinsics.

Define vfadd/vfsub/vfrsub intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang at sifive.com>

Differential Revision: https://reviews.llvm.org/D93291


Compare: https://github.com/llvm/llvm-project/compare/0eb4378290ff...c1dac6bac5b8