[all-commits] [llvm/llvm-project] a2eb07: [VE] Support atomic exchange instructions

[Kazushi Marukawa via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a2eb07aa55405f6e9bca0a0a31681053147e6540
      https://github.com/llvm/llvm-project/commit/a2eb07aa55405f6e9bca0a0a31681053147e6540
  Author: Kazushi (Jam) Marukawa <marukawa at nec.com>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M llvm/lib/Target/VE/VEISelDAGToDAG.cpp
    M llvm/lib/Target/VE/VEISelLowering.cpp
    M llvm/lib/Target/VE/VEISelLowering.h
    M llvm/lib/Target/VE/VEInstrInfo.td
    M llvm/lib/Target/VE/VERegisterInfo.cpp
    A llvm/test/CodeGen/VE/Scalar/atomic.ll
    A llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll
    M llvm/test/CodeGen/VE/Scalar/atomic_load.ll
    M llvm/test/CodeGen/VE/Scalar/atomic_store.ll
    A llvm/test/CodeGen/VE/Scalar/atomic_swap.ll

  Log Message:
  -----------
  [VE] Support atomic exchange instructions

Support atomic exchange and atomic compare and exchange instructions.
Change CAS and TS1AM instructions for ISel patterns.  Add selectADDRzi
pattern for them.  Add TS1AM pseudo instruction also for better ISel.
Add shouldExpandAtomicRMWInIR() function to expand all atomicrmw
instructions except atomicrmw xchg.  Add custom lower for i8/i16
atomicrmw xchg.  Modify replaceFI to support CAS/TS1AM instructions
which use "reg+disp" operands instead of "reg+imm+disp" operands.
And, add several regression tests to check the correctness.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D93161