[all-commits] [llvm/llvm-project] c5ced8: [SVE][CodeGen] Lower scalable floating-point vecto...

[kmclaughlin-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c5ced82c8e49ad629d9c62157655eb31a39c0fad
      https://github.com/llvm/llvm-project/commit/c5ced82c8e49ad629d9c62157655eb31a39c0fad
  Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
  Date:   2020-12-14 (Mon, 14 Dec 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/CodeGen/AArch64/sve-fp-reduce.ll
    A llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll

  Log Message:
  -----------
  [SVE][CodeGen] Lower scalable floating-point vector reductions

Changes in this patch:
-  Minor changes to the LowerVECREDUCE_SEQ_FADD function added by @cameron.mcinally
   to also work for scalable types
- Added TableGen patterns for FP reductions with unpacked types (nxv2f16, nxv4f16 & nxv2f32)
- Asserts added to expandFMINNUM_FMAXNUM & expandVecReduceSeq for scalable types

Reviewed By: cameron.mcinally

Differential Revision: https://reviews.llvm.org/D93050