[all-commits] [llvm/llvm-project] 47321c: [X86][SSE] combineReductionToHorizontal - add vXi8...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 47321c311bdbe0145b9bf45d822185c37b19fa50
      https://github.com/llvm/llvm-project/commit/47321c311bdbe0145b9bf45d822185c37b19fa50
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-12-13 (Sun, 13 Dec 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.h
    M llvm/test/CodeGen/X86/vector-reduce-mul.ll

  Log Message:
  -----------
  [X86][SSE] combineReductionToHorizontal - add vXi8 ISD::MUL reduction handling (PR39709)

Default expansion leads to repeated extensions/truncations to/from vXi16 which shuffle combining and demanded elts can't completely unravel.

Better just to promote (any_extend) the input and perform a vXi16 reduction.

We'll be able to remove a lot of this if we ever get decent legalization support for reduction intrinsics in SelectionDAG.