[all-commits] [llvm/llvm-project] e2006e: [RISCV] Simplify vector instruction handling in RI...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e2006ed0f73e3d7c1545c506f26c330bcc59f60e
      https://github.com/llvm/llvm-project/commit/e2006ed0f73e3d7c1545c506f26c330bcc59f60e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

  Log Message:
  -----------
  [RISCV] Simplify vector instruction handling in RISCVMCInstLower.cpp.

Use RegisterClass::contains instead of going through getMinimalPhysRegClass
and hasSuperClassEq.

Remove the special case for NoRegister. It's identical to the
handling for any other regsiter that isn't VRM2/M4/M8.