[all-commits] [llvm/llvm-project] 12406a: [RISCV] Add (Proposed) Assembler Extend Pseudo-Ins...

[Sam Elliott via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 12406ade0625ffa3939e2fa684293e02eb8791ff
      https://github.com/llvm/llvm-project/commit/12406ade0625ffa3939e2fa684293e02eb8791ff
  Author: Sam Elliott <selliott at lowrisc.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/alu8.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
    M llvm/test/CodeGen/RISCV/rv32Zbbp.ll
    M llvm/test/CodeGen/RISCV/rv64Zbbp.ll
    M llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
    M llvm/test/MC/RISCV/rv32i-aliases-invalid.s
    M llvm/test/MC/RISCV/rv32i-aliases-valid.s
    M llvm/test/MC/RISCV/rv64i-aliases-valid.s

  Log Message:
  -----------
  [RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions

There is an in-progress proposal for the following pseudo-instructions
in the assembler, to complement the existing `sext.w` rv64i instruction:
- sext.b
- sext.h
- zext.b
- zext.h
- zext.w

The `.b` and `.h` variants are available with rv32i and rv64i, and `zext.w` is
only available with `rv64i`.

These are implemented primarily as pseudo-instructions, as these instructions
expand to multiple real instructions. In the case of `zext.b`, this expands to a
single rv32/64i instruction, so it is implemented with an InstAlias (like
`sext.w` is on rv64i).

The proposal is available here: https://github.com/riscv/riscv-asm-manual/pull/61

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D92793