[all-commits] [llvm/llvm-project] e28b6a: [RISCV][NFC] Regenerate RISCV CodeGen tests

[Michael Munday via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e28b6a60bc02d61e50e0da545f337ea482b10240
      https://github.com/llvm/llvm-project/commit/e28b6a60bc02d61e50e0da545f337ea482b10240
  Author: Michael Munday <mike.munday at lowrisc.org>
  Date:   2020-12-09 (Wed, 09 Dec 2020)

  Changed paths:
    M llvm/test/CodeGen/RISCV/alloca.ll
    M llvm/test/CodeGen/RISCV/analyze-branch.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
    M llvm/test/CodeGen/RISCV/atomic-load-store.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/byval.ll
    M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
    M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
    M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
    M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
    M llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
    M llvm/test/CodeGen/RISCV/calls.ll
    M llvm/test/CodeGen/RISCV/copysign-casts.ll
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/double-br-fcmp.ll
    M llvm/test/CodeGen/RISCV/double-calling-conv.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/double-frem.ll
    M llvm/test/CodeGen/RISCV/double-intrinsics.ll
    M llvm/test/CodeGen/RISCV/double-mem.ll
    M llvm/test/CodeGen/RISCV/double-previous-failure.ll
    M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
    M llvm/test/CodeGen/RISCV/exception-pointer-register.ll
    M llvm/test/CodeGen/RISCV/fastcc-float.ll
    M llvm/test/CodeGen/RISCV/fastcc-int.ll
    M llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
    M llvm/test/CodeGen/RISCV/float-br-fcmp.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/float-frem.ll
    M llvm/test/CodeGen/RISCV/float-intrinsics.ll
    M llvm/test/CodeGen/RISCV/float-mem.ll
    M llvm/test/CodeGen/RISCV/fp128.ll
    M llvm/test/CodeGen/RISCV/fp16-promote.ll
    M llvm/test/CodeGen/RISCV/frame-info.ll
    M llvm/test/CodeGen/RISCV/frame.ll
    M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
    M llvm/test/CodeGen/RISCV/ghccc-rv32.ll
    M llvm/test/CodeGen/RISCV/ghccc-rv64.ll
    M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/half-br-fcmp.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-mem.ll
    M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
    M llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll
    M llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll
    M llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr.ll
    M llvm/test/CodeGen/RISCV/large-stack.ll
    M llvm/test/CodeGen/RISCV/mul.ll
    M llvm/test/CodeGen/RISCV/rem.ll
    M llvm/test/CodeGen/RISCV/remat.ll
    M llvm/test/CodeGen/RISCV/rv32Zbb.ll
    M llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
    M llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
    M llvm/test/CodeGen/RISCV/rv64-large-stack.ll
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll
    M llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
    M llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
    M llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
    M llvm/test/CodeGen/RISCV/select-and.ll
    M llvm/test/CodeGen/RISCV/select-or.ll
    M llvm/test/CodeGen/RISCV/shadowcallstack.ll
    M llvm/test/CodeGen/RISCV/shifts.ll
    M llvm/test/CodeGen/RISCV/shrinkwrap.ll
    M llvm/test/CodeGen/RISCV/split-sp-adjust.ll
    M llvm/test/CodeGen/RISCV/srem-lkk.ll
    M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
    M llvm/test/CodeGen/RISCV/stack-realignment.ll
    M llvm/test/CodeGen/RISCV/stack-store-check.ll
    M llvm/test/CodeGen/RISCV/tls-models.ll
    M llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/RISCV/urem-lkk.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/vararg.ll

  Log Message:
  -----------
  [RISCV][NFC] Regenerate RISCV CodeGen tests

Regenerated using:

./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll

This has added comments to spill-related instructions and added @plt to
some symbols.

Differential Revision: https://reviews.llvm.org/D92841