[all-commits] [llvm/llvm-project] af5fd6: [RISCV] Fix missing def operand when creating VSET...

[Fraser Cormack via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: af5fd658952a7f1d9d2a1007217755bd04b4dd4e
      https://github.com/llvm/llvm-project/commit/af5fd658952a7f1d9d2a1007217755bd04b4dd4e
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2020-12-09 (Wed, 09 Dec 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Fix missing def operand when creating VSETVLI pseudos

The register operand was not being marked as a def when it should be. No tests
for this in the main branch as there are not yet any pseudos without a
non-negative VLIndex.

Also change the type of a virtual register operand from unsigned to Register
and adjust formatting.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D92823