[all-commits] [llvm/llvm-project] 95ea50: [VE] Correct LVLGen (LVL instruction insert pass)

[Kazushi Marukawa via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 95ea50e4adf76b75fcc0ad29cacd10642db091a6
      https://github.com/llvm/llvm-project/commit/95ea50e4adf76b75fcc0ad29cacd10642db091a6
  Author: Kazushi (Jam) Marukawa <marukawa at nec.com>
  Date:   2020-12-09 (Wed, 09 Dec 2020)

  Changed paths:
    M llvm/lib/Target/VE/LVLGen.cpp
    M llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll

  Log Message:
  -----------
  [VE] Correct LVLGen (LVL instruction insert pass)

SX Aurora VE uses an intermediate representation similar to VP as its MIR.
VE itself uses invidiual VL register as its own vector length register at
the hardware level.  So, LLVM needs to insert load VL (LVL) instruction just
before vector instructions if the value of VL is changed.  This LVLGen pass
generates LVL instructions for such purpose.  Previously, a bug is pointed
out in D91416.  This patch correct this bug and add a regression test.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D92716