[all-commits] [llvm/llvm-project] 4aa842: [AMDGPU] Add new pseudos for indirect addressing w...

[Austin Kerbow via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 4aa842a800b53806a9e25f03b4e21f6879801a38
      https://github.com/llvm/llvm-project/commit/4aa842a800b53806a9e25f03b4e21f6879801a38
  Author: Austin Kerbow <Austin.Kerbow at amd.com>
  Date:   2020-12-08 (Tue, 08 Dec 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
    A llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll

  Log Message:
  -----------
  [AMDGPU] Add new pseudos for indirect addressing with VGPR Indexing

It is possible for copies or spills to be inserted in the middle of indirect
addressing sequences which use VGPR indexing. Spills to accvgprs could be
effected by the indexing mode.

Add new pseudo instructions that are expanded after register allocation to avoid
the problematic spill or copy placement.

Differential Revision: https://reviews.llvm.org/D91048