[all-commits] [llvm/llvm-project] 98bca0: [RISCV] Add isel patterns for SBCLRI/SBSETI/SBINVI...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 98bca0a60574c4276cfc85833fe29d8f4beff7f6
      https://github.com/llvm/llvm-project/commit/98bca0a60574c4276cfc85833fe29d8f4beff7f6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-12-08 (Tue, 08 Dec 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbs.ll
    M llvm/test/CodeGen/RISCV/rv32Zbt.ll
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll
    M llvm/test/CodeGen/RISCV/rv64Zbs.ll

  Log Message:
  -----------
  [RISCV] Add isel patterns for SBCLRI/SBSETI/SBINVI(W) instruction

We can use these instructions for single bit immediates that are too large for ANDI/ORI/CLRI.

The _10 test cases are to make sure that we still use ANDI/ORI/CLRI for small immediates.

Differential Revision: https://reviews.llvm.org/D92262