[all-commits] [llvm/llvm-project] 3e86fb: [RISCV] Replace custom isel code for RISCVISD::REA...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3e86fbc97189366866aac4286fb9c412c1fb526c
      https://github.com/llvm/llvm-project/commit/3e86fbc97189366866aac4286fb9c412c1fb526c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-12-08 (Tue, 08 Dec 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td

  Log Message:
  -----------
  [RISCV] Replace custom isel code for RISCVISD::READ_CYCLE_WIDE with isel pattern

This node returns 2 results and uses a chain. As long as we use a DAG as part of the pseudo instruction definition where we can use the "set" operator, it looks like tablegen can handle use a pattern for this without a problem. I believe the original implementation was copied from PowerPC.

This also fixes the pseudo instruction so that it is marked as having side effects to match the definition of CSRRS and the RV64 instruction. And we don't need to explicitly clear mayLoad/mayStore since those can be inferred now.

Differential Revision: https://reviews.llvm.org/D92786