[all-commits] [llvm/llvm-project] 5c819e: [RISCV] Form GORCI from (or (rotl/rotr X, Bitwidth...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5c819eb38935cb7ec30ed3c3ef2ffe1ef6420792
      https://github.com/llvm/llvm-project/commit/5c819eb38935cb7ec30ed3c3ef2ffe1ef6420792
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-12-07 (Mon, 07 Dec 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv32Zbp.ll
    M llvm/test/CodeGen/RISCV/rv64Zbp.ll

  Log Message:
  -----------
  [RISCV] Form GORCI from (or (rotl/rotr X, Bitwidth/2), X).

A rotate by half the bitwidth swaps the bottom and top half which is the same as one of the MSB GREVI stage.

We have to do this as a special combine because we prefer to keep (rotl/rotr X, BitWidth/2) as a rotate rather than a single stage GREVI.

Differential Revision: https://reviews.llvm.org/D92286