[all-commits] [llvm/llvm-project] f6dd32: [SVE][CodeGen] Lower scalable masked gathers
kmclaughlin-arm via All-commits
all-commits at lists.llvm.org
Mon Dec 7 04:25:49 PST 2020
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: f6dd32fd3584380730a09b042cfbac852f36eb00
https://github.com/llvm/llvm-project/commit/f6dd32fd3584380730a09b042cfbac852f36eb00
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2020-12-07 (Mon, 07 Dec 2020)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
A llvm/test/CodeGen/AArch64/sve-masked-gather-32b-signed-scaled.ll
A llvm/test/CodeGen/AArch64/sve-masked-gather-32b-signed-unscaled.ll
A llvm/test/CodeGen/AArch64/sve-masked-gather-32b-unsigned-scaled.ll
A llvm/test/CodeGen/AArch64/sve-masked-gather-32b-unsigned-unscaled.ll
A llvm/test/CodeGen/AArch64/sve-masked-gather-64b-scaled.ll
A llvm/test/CodeGen/AArch64/sve-masked-gather-64b-unscaled.ll
A llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
Log Message:
-----------
[SVE][CodeGen] Lower scalable masked gathers
Lowers the llvm.masked.gather intrinsics (scalar plus vector addressing mode only)
Changes in this patch:
- Add custom lowering for MGATHER, using getGatherVecOpcode() to choose the appropriate
gather load opcode to use.
- Improve codegen with refineIndexType/refineUniformBase, added in D90942
- Tests added for gather loads with 32 & 64-bit scaled & unscaled offsets.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D91092
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