[all-commits] [llvm/llvm-project] 5baef6: [RISCV] Initial infrastructure for code generation...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 5baef6353e8819e443d327f84edc9f2d1c8c0c9e
      https://github.com/llvm/llvm-project/commit/5baef6353e8819e443d327f84edc9f2d1c8c0c9e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-12-04 (Fri, 04 Dec 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
    M llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
    A llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir
    A llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll
    A llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll
    A llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll
    A llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll
    A llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll
    M llvm/utils/TableGen/GlobalISelEmitter.cpp

  Log Message:
  -----------
  [RISCV] Initial infrastructure for code generation of the RISC-V V-extension

The companion RFC (http://lists.llvm.org/pipermail/llvm-dev/2020-October/145850.html) gives lots of details on the overall strategy, but we summarize it here:

LLVM IR involving vector types is going to be selected using pseudo instructions (only MachineInstr). These pseudo instructions contain dummy operands to represent the vector type being operated and the vector length for the operation.
These two dummy operands, as set by instruction selection, will be used by the custom inserter to prepend every operation with an appropriate vsetvli instruction that ensures the vector architecture is properly configured for the operation. Not in this patch: later passes will remove the redundant vsetvli instructions.
Register classes of tuples of vector registers are used to represent vector register groups (LMUL > 1).
Those pseudos are eventually lowered into the actual instructions when emitting the MCInsts.
About the patch:

Because there is a bit of initial infrastructure required, this is the minimal patch that allows us to select instructions for 3 LLVM IR instructions: load, add and store vectors of integers. LLVM IR operations have "whole-vector" semantics (as in they generate values for all the elements).

Later patches will extend the information represented in TableGen.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Evandro Menezes <evandro.menezes at sifive.com>
Co-Authored-by: Craig Topper <craig.topper at sifive.com>

Differential Revision: https://reviews.llvm.org/D89449