[all-commits] [llvm/llvm-project] 286daa: [BPF] support atomic instructions

[yonghong-song via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 286daafd65129228e08a1d07aa4ca74488615744
      https://github.com/llvm/llvm-project/commit/286daafd65129228e08a1d07aa4ca74488615744
  Author: Yonghong Song <yhs at fb.com>
  Date:   2020-12-03 (Thu, 03 Dec 2020)

  Changed paths:
    M llvm/lib/Target/BPF/BPFInstrFormats.td
    M llvm/lib/Target/BPF/BPFInstrInfo.td
    M llvm/lib/Target/BPF/BPFMIChecking.cpp
    M llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
    M llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
    M llvm/test/CodeGen/BPF/atomics.ll
    A llvm/test/CodeGen/BPF/atomics_2.ll
    M llvm/test/CodeGen/BPF/xadd.ll

  Log Message:
  -----------
  [BPF] support atomic instructions

Implement fetch_<op>/fetch_and_<op>/exchange/compare-and-exchange
instructions for BPF.  Specially, the following gcc intrinsics
are implemented.
  __sync_fetch_and_add (32, 64)
  __sync_fetch_and_sub (32, 64)
  __sync_fetch_and_and (32, 64)
  __sync_fetch_and_or  (32, 64)
  __sync_fetch_and_xor (32, 64)
  __sync_lock_test_and_set (32, 64)
  __sync_val_compare_and_swap (32, 64)

For __sync_fetch_and_sub, internally, it is implemented as
a negation followed by __sync_fetch_and_add.
For __sync_lock_test_and_set, despite its name, it actually
does an atomic exchange and return the old content.
  https://gcc.gnu.org/onlinedocs/gcc-4.1.1/gcc/Atomic-Builtins.html

For intrinsics like __sync_{add,sub}_and_fetch and
__sync_bool_compare_and_swap, the compiler is able to generate
codes using __sync_fetch_and_{add,sub} and __sync_val_compare_and_swap.

Similar to xadd, atomic xadd, xor and xxor (atomic_<op>)
instructions are added for atomic operations which do not
have return values. LLVM will check the return value for
__sync_fetch_and_{add,and,or,xor}.
If the return value is used, instructions atomic_fetch_<op>
will be used. Otherwise, atomic_<op> instructions will be used.

All new instructions only support 64bit and 32bit with alu32 mode.
old xadd instruction still supports 32bit without alu32 mode.

For encoding, please take a look at test atomics_2.ll.

Differential Revision: https://reviews.llvm.org/D72184