[all-commits] [llvm/llvm-project] f7bc7c: [RISCV] Support Zfh half-precision floating-point ...

[Kai Wang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f7bc7c2981d48525acbf34a26dfb450c6098582c
      https://github.com/llvm/llvm-project/commit/f7bc7c2981d48525acbf34a26dfb450c6098582c
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2020-12-03 (Thu, 03 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/RuntimeLibcalls.def
    M llvm/lib/CodeGen/TargetLoweringBase.cpp
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/test/CodeGen/RISCV/copysign-casts.ll
    A llvm/test/CodeGen/RISCV/half-arith.ll
    A llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
    A llvm/test/CodeGen/RISCV/half-br-fcmp.ll
    A llvm/test/CodeGen/RISCV/half-convert.ll
    A llvm/test/CodeGen/RISCV/half-fcmp.ll
    A llvm/test/CodeGen/RISCV/half-imm.ll
    A llvm/test/CodeGen/RISCV/half-intrinsics.ll
    A llvm/test/CodeGen/RISCV/half-isnan.ll
    A llvm/test/CodeGen/RISCV/half-mem.ll
    A llvm/test/CodeGen/RISCV/half-select-fcmp.ll
    A llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
    A llvm/test/CodeGen/RISCV/rv64f-half-convert.ll
    A llvm/test/CodeGen/RISCV/zfh-imm.ll
    M llvm/test/MC/RISCV/rv32i-invalid.s
    A llvm/test/MC/RISCV/rv32zfh-invalid.s
    A llvm/test/MC/RISCV/rv32zfh-valid.s
    A llvm/test/MC/RISCV/rv64zfh-invalid.s
    A llvm/test/MC/RISCV/rv64zfh-valid.s
    A llvm/test/MC/RISCV/rvzfh-aliases-valid.s
    A llvm/test/MC/RISCV/rvzfh-pseudos.s

  Log Message:
  -----------
  [RISCV] Support Zfh half-precision floating-point extension.

Support "Zfh" extension according to
https://github.com/riscv/riscv-isa-manual/blob/zfh/src/zfh.tex

Differential Revision: https://reviews.llvm.org/D90738


  Commit: 432d05174ed00a217c0ad37e2e823154624c1311
      https://github.com/llvm/llvm-project/commit/432d05174ed00a217c0ad37e2e823154624c1311
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2020-12-03 (Thu, 03 Dec 2020)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/lib/Basic/Targets/RISCV.h
    M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
    M clang/test/Driver/riscv-arch.c
    M clang/test/Preprocessor/riscv-target-features.c

  Log Message:
  -----------
  [RISCV] Handle zfh in the arch string.

Differential Revision: https://reviews.llvm.org/D91315


Compare: https://github.com/llvm/llvm-project/compare/3b18a594c771...432d05174ed0