[all-commits] [llvm/llvm-project] 94ead0: [InstCombine] Improve vector undef handling for se...

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  Branch: refs/heads/temp-test-main
  Home:   https://github.com/llvm/llvm-project
  Commit: 94ead0190ff18be337c5c84abccc315fd68f41fc
      https://github.com/llvm/llvm-project/commit/94ead0190ff18be337c5c84abccc315fd68f41fc
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2020-12-01 (Tue, 01 Dec 2020)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
    M llvm/test/Transforms/InstCombine/sext.ll
    M llvm/test/Transforms/InstCombine/trunc.ll

  Log Message:
  -----------
  [InstCombine] Improve vector undef handling for sext(ashr(shl(trunc()))) fold, 2

If the shift amount was undef for some lane, the shift amount in opposite
shift is irrelevant for that lane, and the new shift amount for that lane
can be undef.


  Commit: fd679107d670d8fd31b62245b433187b4d72a9d0
      https://github.com/llvm/llvm-project/commit/fd679107d670d8fd31b62245b433187b4d72a9d0
  Author: Bhramar Vatsa <Bhramar.Vatsa at synopsys.com>
  Date:   2020-12-01 (Tue, 01 Dec 2020)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    M llvm/test/Transforms/InstCombine/and.ll

  Log Message:
  -----------
  [InstCombine] Optimize away the unnecessary multi-use sign-extend

C.f. https://bugs.llvm.org/show_bug.cgi?id=47765

Added a case for handling the sign-extend (Shl+AShr) for multiple uses,
to optimize it away for an individual use,
when the demanded bits aren't affected by sign-extend.

https://rise4fun.com/Alive/lgf

Reviewed By: lebedev.ri

Differential Revision: https://reviews.llvm.org/D91343


Compare: https://github.com/llvm/llvm-project/compare/6bf84871e938...fd679107d670