[all-commits] [llvm/llvm-project] 6dbd0d: [DAG] Move vselect(icmp_ult, -1, add(x, y)) -> uadd...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/temp-test-main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6dbd0d36a1729e129bb11647b91bdb615d42c98c
      https://github.com/llvm/llvm-project/commit/6dbd0d36a1729e129bb11647b91bdb615d42c98c
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-12-01 (Tue, 01 Dec 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sat-add.ll
    M llvm/test/CodeGen/PowerPC/sat-add.ll
    M llvm/test/CodeGen/X86/sat-add.ll
    M llvm/test/CodeGen/X86/uadd_sat_vec.ll

  Log Message:
  -----------
  [DAG] Move vselect(icmp_ult, -1, add(x,y)) -> uaddsat(x,y) to DAGCombine (PR40111)

Move the X86 VSELECT->UADDSAT fold to DAGCombiner - there's nothing target specific about these folds.

The SSE42 test diffs are relatively benign - its avoiding an extra constant load in exchange for an extra xor operation - there are extra register moves, which is annoying as all those operations should commute them away.

Differential Revision: https://reviews.llvm.org/D91876