[all-commits] [llvm/llvm-project] 7923d7: [ARM] PREDICATE_CAST demanded bits

[David Green via All-commits]

  Branch: refs/heads/temp-test-main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7923d71b4a7a88f97c8a3efe1eb1473a4b2f5bf3
      https://github.com/llvm/llvm-project/commit/7923d71b4a7a88f97c8a3efe1eb1473a4b2f5bf3
  Author: David Green <david.green at arm.com>
  Date:   2020-12-01 (Tue, 01 Dec 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-constfold.ll

  Log Message:
  -----------
  [ARM] PREDICATE_CAST demanded bits

The PREDICATE_CAST node is used to model moves between MVE predicate
registers and gpr's, and eventually become a VMSR p0, rn. When moving to
a predicate only the bottom 16 bits of the sources register are
demanded. This adds a simple fold for that, allowing it to potentially
remove instructions like uxth.

Differential Revision: https://reviews.llvm.org/D92213


  Commit: 09d82fa95f4561a6a2ce80bce00209018ba70c24
      https://github.com/llvm/llvm-project/commit/09d82fa95f4561a6a2ce80bce00209018ba70c24
  Author: David Green <david.green at arm.com>
  Date:   2020-12-01 (Tue, 01 Dec 2020)

  Changed paths:
    M llvm/test/CodeGen/AArch64/O3-pipeline.ll

  Log Message:
  -----------
  [AArch64] Update pass pipeline test. NFC


Compare: https://github.com/llvm/llvm-project/compare/839c9635edce...09d82fa95f45