[all-commits] [llvm/llvm-project] f6150a: [SelectionDAGBuilder] Update signature of `getRegs...

[Francesco Petrogalli via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f6150aa41a48ac8b5372fe4d6ccdfff96e432431
      https://github.com/llvm/llvm-project/commit/f6150aa41a48ac8b5372fe4d6ccdfff96e432431
  Author: Francesco Petrogalli <francesco.petrogalli at arm.com>
  Date:   2020-11-30 (Mon, 30 Nov 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
    A llvm/test/CodeGen/AArch64/sdag-no-typesize-warnings-regandsizes.ll

  Log Message:
  -----------
  [SelectionDAGBuilder] Update signature of `getRegsAndSizes()`.

The mapping between registers and relative size has been updated to
use TypeSize to account for the size of scalable EVTs.

The patch is a NFCI, if not for the fact that with this change the
function `getUnderlyingArgRegs` does not raise a warning for implicit
conversion of `TypeSize` to `unsigned` when generating machine code
from the test added to the patch.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D92096