[all-commits] [llvm/llvm-project] 76d102: [RISCV] Custom legalize bswap/bitreverse to GREVI ...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 76d1026b59bd04bd31645ab37dd82d1d89daa6d9
      https://github.com/llvm/llvm-project/commit/76d1026b59bd04bd31645ab37dd82d1d89daa6d9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-30 (Mon, 30 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbp.ll
    M llvm/test/CodeGen/RISCV/rv64Zbp.ll

  Log Message:
  -----------
  [RISCV] Custom legalize bswap/bitreverse to GREVI with Zbp extension to enable them to combine with other GREVI instructions

This enables bswap/bitreverse to combine with other GREVI patterns or each other without needing to add more special cases to the DAG combine or new DAG combines.

I've also enabled the existing GREVI combine for GREVIW so that it can pick up the i32 bswap/bitreverse on RV64 after they've been type legalized to GREVIW.

Differential Revision: https://reviews.llvm.org/D92253