[all-commits] [llvm/llvm-project] 77e25b: [RISCV] Remove RV32 HwMode. Use DefaultMode for RV32

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 77e25b5bc8860e23395f617dcca4940489f6355c
      https://github.com/llvm/llvm-project/commit/77e25b5bc8860e23395f617dcca4940489f6355c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-20 (Fri, 20 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td

  Log Message:
  -----------
  [RISCV] Remove RV32 HwMode. Use DefaultMode for RV32

Prior to this the DefaultMode was never selected, but RISCVGenDAGISel.inc, RISCVGenRegisterInfo.inc, RISCVGenGlobalISel.inc all ended up with extra table entries for that mode.

This patch removes the RV32 and uses DefaultMode for RV32. This impressively reduces the size of my release+asserts llc binary by about 270K. About 15K from RISCVGenDAGISel.inc, 1-2K from RISCVGenRegisterInfo.inc, but the vast majority from RISCVGenGlobalISel.inc.

Differential Revision: https://reviews.llvm.org/D90973