[all-commits] [llvm/llvm-project] 6a1d8b: [RISCV] Custom type legalize i32 bswap/bitreverse ...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 6a1d8b91ed730e01f471efa5f98838615346cd8b
      https://github.com/llvm/llvm-project/commit/6a1d8b91ed730e01f471efa5f98838615346cd8b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-20 (Fri, 20 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv64Zbp.ll

  Log Message:
  -----------
  [RISCV] Custom type legalize i32 bswap/bitreverse to GREVIW on RV64 with Zbp extension

Previously we required a sra to pattern match these properly in isel. If the consumer didn't need the result sign extended we'll have an srl instead of sra and fail to match.

This patch switches to custom legalizing to GREVIW using portions of D91259.

Differential Revision: https://reviews.llvm.org/D91457